A summary of options is included below.
-Q suppress printing of banner (copyright, disclaimer, version)
-T suppress printing of footer (log hash, version, timing statistics)
-q quiet operation. only write error message to console use this option twice to also quiet warning
messages
-v<level>
print log headers up to level <level> to the console. (implies -q)
-t annotate all log messages with a time stamp
-d print more detailed timing stats at exit
-llogfile
write log messages to the specified file
-Llogfile
like -l but open log file in line buffered mode
-ooutfile
write the design to the specified file on exit
-bbackend
use this backend for the output file specified on the command line
-ffrontend
use the specified frontend for the input files on the command line
-H print the command list
-hcommand
print the help message for the specified command
-sscriptfile
execute the commands in the script file
-ctcl_scriptfile
execute the commands in the tcl script file (see 'help tcl' for details)
-pcommand
execute the commands
-mmodule_file
load the specified module (aka plugin)
-X enable tracing of core data structure changes. for debugging
-M will slightly randomize allocated pointer addresses. for debugging
-A will call abort() at the end of the script. for debugging
-D<header_id>[:<filename>]
dump the design when printing the specified log header to a file. yosys_dump_<header_id>.il is
used as filename if none is specified. Use 'ALL' as <header_id> to dump at every header.
-Wregex
if a warning message matches the regex, it is printed as regular message instead.
-eregex
if a warning message matches the regex, it is printed as error message instead and the tool
terminates with a nonzero return code.
-V print version information and exit
-Edepsfile
write a Makefile dependencies file with in- and output file names
-S The option -S is an alias for the "synth" command, a default script for transforming the Verilog
input to a gate-level netlist. For example:
yosys -o output.blif -S input.v